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general description the MAX1586/max1587 power-management ics are optimized for devices using intel x-scale micro- processors, including third-generation smart cell phones, pdas, internet appliances, and other portable devices requiring substantial computing and multime- dia capability at low power. the ics integrate seven high-performance, low-operating- current power supplies along with supervisory and man- agement functions. regulator outputs include three step- down dc-dc outputs, three linear regulators, and a seventh always-on output. dc-dc converter outputs power i/o, dram, and the cpu core. the i/o supply can be preset to 3.3v or 3.0v, or can be adjusted to other val- ues. the dram supply on the MAX1586a and max1587a is preset for 1.8v or 2.5v, while the MAX1586b dram supply is preset for 3.3v or 2.5v. the dram supply on all parts can also be adjusted with external resistors. the cpu core supply is serial programmed for dynamic volt- age management. linear-regulated outputs are provided for sram, pll, and usim supplies. to minimize sleep-state quiescent current, critical power supplies have bypass ?leep?ldos that can be activated to minimize battery drain when output current is very low. other functions include separate on/off con- trol for all dc-dc converters, low-battery and dead-bat- tery detection, a reset and power-ok output, a backup- battery input, and a two-wire serial interface. all dc-dc outputs use fast, 1mhz pwm switching and small external components. they operate with fixed-fre- quency pwm control and automatically switch from pwm to skip-mode operation at light loads to reduce operating current and extend battery life. the core out- put is capable of operating in forced-pwm mode at all loads to minimize ripple and noise. a 2.6v to 5.5v input voltage range allows 1-cell lithium-ion (li+), 3-cell nimh, or a regulated 5v input. the max1587 is avail- able in a tiny 6mm x 6mm, 40-pin thin qfn package. the MAX1586 features an additional linear regulator (v6) for vcc_usim and low-battery and dead- battery comparators. the MAX1586 is available in a 7mm x 7mm, 48-pin thin qfn package. applications pda, palmtop, and wireless handhelds third-generation smart cell phones internet appliances and web-books features ? six regulators in one package: step-down dc-dc for i/o at 1.3a step-down dc-dc for memory at 0.9a step-down serial-programmed dc-dc for core three ldo outputs for sram, pll, and usim always-on output for vcc_batt ? low operating current 60? in sleep mode (sleep ldos on) 130? with dc-dcs on (core off) 200? all regulators on, no load 5? shutdown current ? optimized for x-scale processors ? backup-battery input ? separate on controls for any desired power sequencing ? 1mhz pwm switching allows small external components ? tiny 6mm x 6mm, 40-pin and 7mm x 7mm, 48-pin thin qfn packages MAX1586a/MAX1586b/max1587a high-efficiency, low-i q pmics with dynamic core for pdas and smart phones ________________________________________________________________ maxim integrated products 1 ordering information MAX1586 max1587 v1 v2 v3 v4 v5 v6 v7 vcc_io 3.3v vcc_mem 2.5v vcc_core 0.8v to 1.3v vcc_usim 0v, 1.8v, 3.0v main battery vcc_pll 1.3v vcc_sram 1.1v backup battery in bkbt mr rso vcc_batt pok nreset nvcc_fault sys_en pwr_en on1-2 on3-6 nbatt_fault dbo simplified functional diagram 19-3089; rev 0; 12/03 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available pin configurations appear at end of data sheet. part temp range pin-package MAX1586a etm -40? to +85? 48 thin qfn 7mm x 7mm MAX1586b etm -40? to +85? 48 thin qfn 7mm x 7mm max1587a etl -40? to +85? 40 thin qfn 6mm x 6mm x-scale is a trademark of intel corp.
MAX1586a/MAX1586b/max1587a high-efficiency, low-i q pmics with dynamic core for pdas and smart phones 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v in = 3.6v, v bkbt = 3.0v, v lbi = 1.1v, v dbi = 1.35v, circuit of figure 5, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25 c.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. in, in45, in6, mr , lbo , dbo , rso , pok, scl, sda, bkbt, v7, slp , srad, pwm3 to gnd...............-0.3v to +6v ref, cc_, on_, fb_, dbi, lbi, v1, v2, ramp, byp, mr to gnd ...........................................-0.3v to (v in + 0.3v) pv1, pv2, pv3, slpin to in...................................-0.3v to +0.3v v4, v5 to gnd ..........................................-0.3v to (v in45 + 0.3v) v6 to gnd ..................................................-0.3v to (v in6 + 0.3v) pv1 to pg1 ............................................................-0.3v to +6.0v pv2 to pg2 ............................................................-0.3v to +6.0v pv3 to pg3 ............................................................-0.3v to +6.0v lx1 continuous current....................................-1.30a to +1.30a lx2 continuous current........................................-0.9a to +0.9a lx3 continuous current........................................-0.5a to +0.5a pg1, pg2, pg3 to gnd.........................................-0.3v to +0.3v v1, v2, v4, v5, v6 output short-circuit duration.......continuous continuous power dissipation (t a = +70?) 6mm x 6mm 40-pin thin qfn (derate 26.3mw/? above +70?) ...........................2105mw 7mm x 7mm 48-pin thin qfn (derate 26.3mw/? above +70?) ...........................2105mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter conditions min typ max units pv1, pv2, pv3, slpin, in supply voltage range pv1, pv2, pv3, in, and slpin must connect together externally 2.6 5.5 v in45, in6 supply voltage range 2.4 5.5 v v in rising 2.25 2.40 2.55 in undervoltage-lockout (uvlo) threshold v in falling 2.200 2.35 2.525 v MAX1586 32 only v7 on, v in below dbi threshold v in = 3.0v max1587 5 MAX1586 130 reg1 and reg2 on in switch mode, reg3 off max1587 130 MAX1586 60 reg1 and reg2 on in sleep mode, reg3 off max1587 60 MAX1586 225 quiescent current no load (i pv1 + i pv2 + i pv3 + i in + i slpin + i in45 + i in6 ) all regs on max1587 200 ? on1 = 0 4 bkbt input current on1 = in 0.8 ? ref output voltage 0 to 10? load 1.2375 1.25 1.2625 v synchronous-buck pwm reg1 fb1 = gnd, 3.6v v pv1 5.5v, load = 0 to 1200ma 3.25 3.3 3.35 reg1 voltage accuracy fb1 = in, 3.6v v pv1 5.5v, load = 0 to 1200ma 2.955 3.0 3.045 v fb1 voltage accuracy fb1 used with external resistors, 3.6v v pv1 5.5v, load = 0 to 1200ma 1.225 1.25 1.275 v fb1 input current fb1 used with external resistors 100 na error-amplifier transconductance referred to fb 87 ? load = 800ma 180 280 dropout voltage (note 1) load = 1300ma 293 450 mv
MAX1586a/MAX1586b/max1587a high-efficiency, low-i q pmics with dynamic core for pdas and smart phones _______________________________________________________________________________________ 3 parameter conditions min typ max units i lx1 = -180ma 0.18 0.3 p-channel on-resistance i lx1 = -180ma, v pv1 = 2.6v 0.21 0.35 ? i lx1 = 180ma 0.13 0.225 n-channel on-resistance i lx1 = 180ma, v pv1 = 2.6v 0.15 0.25 ? current-sense transresistance 0.5 v/a p-channel current-limit threshold -1.55 -1.80 -2.10 a pwm skip-mode transition load current decreasing load current (note 2) 30 ma out1 maximum output current 2.6v v pv1 5.5v (note 3) 1.20 a lx1 leakage current v pv1 = 5.5v, lx1 = gnd or pv1, v on1 = 0v -20 +0.1 +20 ? synchronous-buck pwm reg2 fb2 = gnd, 3.6v v pv2 5.5v, load = 0 to 900ma 2.463 2.5 2.537 MAX1586a, max1587a, fb2 = in, 3.6v v pv2 5.5v, load = 0 to 900ma 1.773 1.8 1.827 reg2 voltage accuracy MAX1586b, fb2 = in, 3.6v v pv2 5.5v, load = 0 to 900ma 3.25 3.3 3.35 v fb2 voltage accuracy fb2 used with external resistors, 3.6v v pv2 5.5v, load = 0 to 900ma 1.231 1.25 1.269 v fb2 input current fb2 used with external resistors, v fb2 = 1.25v 100 na error-amplifier transconductance referred to fb 87 ? dropout voltage load = 900ma (note 1) 243 380 mv i lx2 = -180ma 0.225 0.375 p-channel on-resistance i lx2 = -180ma, vpv2 = 2.6v 0.26 0.425 ? i lx2 = 180ma 0.15 0.25 n-channel on-resistance i lx2 = 180ma, vpv2 = 2.6v 0.17 0.275 ? current-sense transresistance 0.75 v/a p-channel current-limit threshold -1.1 -1.275 -1.50 a pwm skip-mode transition load current decreasing load current (note 2) 30 ma out2 maximum output current 2.6v v pv2_ 5.5v (note 3) 0.9 a lx2 leakage current v pv2_ = 5.5v, lx2 = gnd or pv2, v on2 = 0v -10 +0.1 +10 ? synchronous-buck pwm reg3 reg3 from 1.3v to 1.475v, 2.6v v pv3 _ 5.5v, load = 0 to 400ma -1.5 +1.5 reg3 output voltage accuracy reg3 from 0.70v to 1.275v, 2.6v v pv3 _ 5.5v, load = 0 to 500ma -2 +2 % error-amplifier transconductance 68 ? electrical characteristics (continued) (v in = 3.6v, v bkbt = 3.0v, v lbi = 1.1v, v dbi = 1.35v, circuit of figure 5, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25 c.)
MAX1586a/MAX1586b/max1587a high-efficiency, low-i q pmics with dynamic core for pdas and smart phones 4 _______________________________________________________________________________________ parameter conditions min typ max units i lx3 = -180ma 0.225 0.375 p-channel on-resistance i lx2 = -180ma, v pv3 = 2.6v 0.26 0.425 ? i lx3 = 180ma 0.15 0.25 n-channel on-resistance i lx3 = 180ma, v pv3 = 2.6v 0.17 0.275 ? current-sense transresistance 1.25 v/a p-channel current-limit threshold -0.60 -0.7 -0.85 a pwm skip-mode transition load current decreasing load current (note 2) 30 ma out3 maximum output current 2.6v v pv3_ 5.5v (note 3) 0.5 a lx3 leakage current v pv3_ = 5.5v, lx3 = gnd or pv2, v on3 = 0v -10 +0.1 +10 ? ldos v4, v5, v6, v1 sleep, v2 sleep, and v7 output v4, v5, v6, v1 sleep, v2 sleep output current 35 ma v7 output current 30 ma reg4 output voltage load = 0.1 to 35ma 1.261 1.3 1.339 v reg4 noise with 1? c out and 0.01? c byp 15 ?rms reg5 output voltage load = 0.1ma to 35ma 1.067 1.1 1.133 v in45, in6 input voltage range 2.4 5.5 v 0v se tti ng ( ei t her on 6 l ow or ser i al p r og r am m ed ) 0 1.8v setting, load = 0.1ma to 35ma 1.746 1.8 1.854 2.5v setting, load = 0.1ma to 35ma 2.425 2.5 2.575 reg6 output voltage (por default to 0v, set by serial input) MAX1586 3.0v setting, load = 0.1ma to 35ma 2.91 3.0 3.09 v v1 on and in regulation v v1 v7 output voltage v1 off v bkbt v v1 and v2 sleep output voltage accuracy set to same output voltage as reg1 and reg2 -3.0 +3.0 % v1 and v2 sleep dropout voltage load = 20ma 75 150 mv v6 dropout voltage m ax 1586 3v m od e, l oad = 30m a, 2.5v m od e, l oad = 30m a 110 200 mv v7 switch voltage drop load = 20ma, v bkbt = v v1 = 3.0v 100 200 mv v4, v5, v6 output current limit 40 90 ma bkbt leakage 1 ? oscillator pwm switching frequency 0.93 1 1.07 mhz supervisory/management functions rising 92 94.75 97 pok trip threshold (note 4) falling 88.5 90.5 92.5 % electrical characteristics (continued) (v in = 3.6v, v bkbt = 3.0v, v lbi = 1.1v, v dbi = 1.35v, circuit of figure 5, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25 c.)
MAX1586a/MAX1586b/max1587a high-efficiency, low-i q pmics with dynamic core for pdas and smart phones _______________________________________________________________________________________ 5 parameter conditions min typ max units lbi = in (for preset) 3.51 3.6 3.69 lbi threshold (falling) MAX1586 hysteresis is 5% (typ) with resistors at lbi 0.98 1.00 1.02 v dbi = in (for preset) 3.024 3.15 3.276 dbi threshold (falling) MAX1586 hysteresis is 5% (typ) with resistors at lbi 1.208 1.232 1.256 v rso threshold (falling) voltage on reg7, hysteresis is 5% (typ) 2.25 2.41 2.56 v rso deassert delay 61 65.5 70 ms lbi input bias current MAX1586 -50 -5 na dbi input bias current MAX1586 15 50 na thermal-shutdown temperature t j rising +160 ? thermal-shutdown hysteresis 15 ? logic inputs and outputs lbo , dbo , pok, rso , sda output low level 2.6v v7 5.5v, sinking 1ma 0.4 v lbo , dbo , pok, rso output low level v7 = 1v, sinking 100? 0.4 v lbo , dbo , pok, rso output-high leakage current pin = 5.5v 0.2 ? on_, scl, sda, slp , pwm3, mr , srad input high level 2.6v v in 5.5v 1.6 v on_, scl, sda, slp , pwm3, mr , srad input low level 2.6v v in 5.5v 0.4 v on_, scl, sda, slp , pwm3, mr , srad input leakage current pin = gnd, 5.5v 1 1 ? serial interface clock frequency 400 khz bus-free time between start and stop 1.3 ? h ol d ti m e rep eated s t art c ond i ti on 0.6 ? clk low period 1.3 ? clk high period 0.6 ? s etup ti m e rep eated s t art c ond i ti on 0.6 ? data hold time 0s data setup time 100 ns maximum pulse width of spikes that must be suppressed by the input filter of both data and clk signals 50 ns setup time for stop condition 0.6 ? electrical characteristics (continued) (v in = 3.6v, v bkbt = 3.0v, v lbi = 1.1v, v dbi = 1.35v, circuit of figure 5, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25 c.)
MAX1586a/MAX1586b/max1587a high-efficiency, low-i q pmics with dynamic core for pdas and smart phones 6 _______________________________________________________________________________________ parameter conditions min max units pv1, pv2, pv3, slpin, in supply voltage range pv1, pv2, pv3, in, and slpin must connect together externally 2.6 5.5 v in45, in6 supply voltage range 2.4 5.5 v v in rising 2.25 2.55 in undervoltage-lockout (uvlo) threshold v in falling 2.200 2.525 v synchronous-buck pwm reg1 fb1 = gnd, 3.6v v pv1 5.5v, load = 0 to 1300ma 3.25 3.35 reg1 voltage accuracy fb1 = in, 3.6v v pv1 5.5v, load = 0 to 1300ma 2.955 3.045 v fb1 voltage accuracy fb1 used with external resistors, 3.6v v pv1 5.5v, load = 0 to 1300ma 1.231 1.269 v fb1 input current fb1 used with external resistors 100 na load = 800ma (note 1) 280 dropout voltage load = 1300ma (note 1) 450 mv i lx1 = -180ma 0.3 p-channel on-resistance i lx1 = -180ma, v pv1 = 2.6v 0.35 ? i lx1 = 180ma 0.225 n-channel on-resistance i lx1 = 180ma, v pv1 = 2.6v 0.25 ? p-channel current-limit threshold -1.55 -2.10 a out1 maximum output current 2.6v v pv1 5.5v (note 3) 1.30 a lx1 leakage current v pv1 = 5.5v, lx1 = gnd or pv1, v on1 = 0v -10 +10 ? synchronous-buck pwm reg2 fb2 = gnd, 3.6v v pv2 5.5v, load = 0 to 900ma 2.463 2.537 MAX1586a, max1587a, fb2 = in, 3.6v v pv2 5.5v, load = 0 to 900ma 1.773 1.827 reg2 voltage accuracy MAX1586b, fb2 = in, 3.6v v pv2 5.5v, load = 0 to 900ma 3.25 3.35 v fb2 voltage accuracy fb2 used with external resistors, 3.6v v pv2 5.5v, load = 0 to 900ma 1.231 1.269 v fb2 input current fb2 used with external resistors, v fb2 = 1.25v 100 na dropout voltage load = 900ma (note 1) 380 mv i lx2 = -180ma 0.375 p-channel on-resistance i lx2 = -180ma, v pv2 = 2.6v 0.425 ? i lx2 = -180ma 0.25 n-channel on-resistance i lx2 = -180ma, v pv2 = 2.6v 0.275 ? p-channel current-limit threshold -1.1 -1.50 a out2 maximum output current 2.6v v pv2_ 5.5v (note 3) 0.9 a lx2 leakage current v pv2 = 5.5v, lx2 = gnd or pv2, v on2 = 0v -10 +10 ? electrical characteristics (v in = 3.6v, v bkbt = 3.0v, v lbi = 1.1v, v dbi = 1.35v, circuit of figure 5, t a = -40? to +85? , unless otherwise noted.) (note 5)
MAX1586a/MAX1586b/max1587a high-efficiency, low-i q pmics with dynamic core for pdas and smart phones _______________________________________________________________________________________ 7 parameter conditions min max units synchronous-buck pwm reg3 reg3 from 1.3v to 1.475v, 2.6v v pv3_ 5.5v, load = 0 to 500ma -1.5 +1.5 reg3 output voltage accuracy reg3 from 0.70v to 1.275v, 2.6v v pv3_ 5.5v, load = 0 to 500ma -2 +2 % i lx3 = -180ma 0.375 p-channel on-resistance i lx2 = -180ma, v pv3 = 2.6v 0.425 ? i lx3 = 180ma 0.25 n-channel on-resistance i lx3 = 180ma, v pv3 = 2.6v 0.275 ? p-channel current-limit threshold -0.60 +0.85 a out3 maximum output current 2.6v v pv3_ 5.5v (note 3) 0.4 a lx3 leakage current v pv3 = 5.5v, lx3 = gnd or pv2, v on3 = 0v -10 +10 ? ldos v4, v5, v6, v1 sleep, v2 sleep, and v7 output v4, v5, v6, v1 sleep, v2 sleep output current 35 ma v7 output current 30 ma reg4 output voltage load = 0.1ma to 35ma 1.254 1.346 v reg5 output voltage load = 0.1ma to 35ma 1.061 1.139 v in45, in6 input voltage range 2.4 5.5 v 1.8v setting, load = 0.1ma to 35ma 1.737 1.863 2.5v setting, load = 0.1ma to 35ma 2.412 2.588 reg6 output voltage (por default to 0v, set by serial input) MAX1586 3.0v setting, load = 0.1ma to 35ma 2.895 3.105 v v1 and v2 sleep output voltage accuracy set to same output voltage as reg1 and reg2 -3.5 +3.5 % v1 and v2 sleep dropout voltage load = 20ma 150 mv v6 dropout voltage m ax 1586 3v m od e, l oad = 30m a; 2.5v m od e, l oad = 30m a 200 mv v7 switch voltage drop load = 20ma, v bkbt = v v1 = 3.0v 200 mv v4, v5, v6 output current limit 40 ma bkbt leakage 1 ? oscillator pwm switching frequency 0.93 1.07 mhz supervisory/management functions rising 92 97 pok trip threshold (note 4) falling 88.5 92.5 % lbi = in (for preset) 3.51 3.69 lbi threshold (falling) MAX1586, hysteresis is 5% (typ) with resistors at lbi 0.98 1.02 v dbi = in (for preset) 2.993 3.307 dbi threshold (falling) MAX1586, hysteresis is 5% (typ) with resistors at lbi 1.208 1.256 v rso threshold (falling) voltage on reg7, hysteresis is 5% (typ) 2.25 2.60 v electrical characteristics (continued) (v in = 3.6v, v bkbt = 3.0v, v lbi = 1.1v, v dbi = 1.35v, circuit of figure 5, t a = -40? to +85? , unless otherwise noted.) (note 5)
MAX1586a/MAX1586b/max1587a high-efficiency, low-i q pmics with dynamic core for pdas and smart phones 8 _______________________________________________________________________________________ parameter conditions min max units rso deassert delay 62 69 ms lbi input bias current MAX1586 -50 na dbi input bias current MAX1586 75 na logic inputs and outputs lbo , dbo , pok, rso , sda output low level 2.6v v7 5.5v, sinking 1ma 0.4 v lbo , dbo , pok, rso , sda output low level v7 = 1v, sinking 100? 0.4 v lbo , dbo , pok, rso output-high leakage current pin = 5.5v 0.2 ? on_, scl, sda, slp , pwm3, mr , srad input high level 2.6v v in 5.5v 1.6 v on_, scl, sda, slp , pwm3, mr , srad input low level 2.6v v in 5.5v 0.4 v on_, scl, sda, slp , pwm3, mr , srad input leakage current pin = gnd, 5.5v 1 1 ? serial interface clock frequency 400 khz bus-free time between start and stop 1.3 ? hold time repeated start condition 0.6 ? clk low period 1.3 ? clk high period 0.6 ? setup time repeated start condition 0.6 ? data hold time 0s data setup time 100 ns setup time for stop condition 0.6 ? electrical characteristics (continued) (v in = 3.6v, v bkbt = 3.0v, v lbi = 1.1v, v dbi = 1.35v, circuit of figure 5, t a = -40? to +85? , unless otherwise noted.) (note 5)
MAX1586a/MAX1586b/max1587a high-efficiency, low-i q pmics with dynamic core for pdas and smart phones _______________________________________________________________________________________ 9 note 1: dropout voltage is guaranteed by the p-channel switch resistance and assumes a maximum inductor resistance of 45m ? . note 2: the pwm-skip-mode transition has approximately 10ma of hysteresis. note 3: the maximum output current is guaranteed by the following equation: where: and r n = n-channel synchronous rectifier r ds(on) r p = p-channel power switch r ds(on) r l = external inductor esr i out(max) = maximum required load current f = operating frequency minimum l = external inductor value i lim can be substituted for i out(max) (desired) when solving for d. this assumes that the inductor ripple current is small relative to the absolute value. note 4: pok only indicates the status of supplies that are enabled (except v7). when a supply is turned off, pok does not trigger low. when a supply is turned on, pok immediately goes low until that supply reaches regulation. pok is forced low when all supplies (except v7) are disabled. note 5: specifications to -40? are guaranteed by design, not production tested. d vi rr vi rr out out max n l in out max n p = ++ + ? () () () () i i vd xfxl rr d xfxl out lim out nl max () () () = ? ? ++ ? 1 2 1 1 2 electrical characteristics (continued)
MAX1586a/MAX1586b/max1587a high-efficiency, low-i q pmics with dynamic core for pdas and smart phones 10 ______________________________________________________________________________________ t ypical operating characteristics (circuit of figure 5, v in = 3.6v, t a = +25 c, unless otherwise noted.) 100 0.1 1 10 100 1000 10,000 90 80 70 60 50 40 reg1 3.3v output efficiency vs. load current MAX1586a/86b/87a toc01 load current (ma) efficiency (%) v in = 3.6v v in = 4.0v v in = 5.0v 100 40 0.1 10 100 1100 0 reg2 2.5v output efficiency vs. load current MAX1586a/86b/87a toc02 load current (ma) efficiency (%) 50 60 70 80 90 v in = 3.6v v in = 4.0v v in = 5.0v 100 40 0.1 10 100 1 1000 reg3 1.3v output efficiency vs. load current MAX1586a/86b/87a toc03 load current (ma) efficiency (%) 50 60 70 80 90 v in = 3.6v v in = 4.0v v in = 5.0v 100 40 0.1 10 100 1 1000 reg3 1.3v output with forced-pwm efficiency vs. load current MAX1586a/86b/87a toc04 load current (ma) efficiency (%) 50 60 70 80 90 v in = 3.6v v in = 5.0v v in = 4.0v reg1 sleep ldo 3.3v output efficiency vs. load current MAX1586a/86b/87a toc05 load current (ma) efficiency (%) 100 40 50 60 70 80 90 0.1 1 10 v in = 3.6v v in = 4.0v v in = 5.0v reg2 sleep ldo 2.5v output efficiency vs. load current MAX1586a/86b/87a toc06 load current (ma) efficiency (%) 90 30 40 50 60 70 80 0.1 1 10 v in = 3.6v v in = 4.0v v in = 5.0v 0 20 140 100 180 220 02 1345 quiescent current vs. supply voltage MAX1586a/86b/87a toc07 input voltage (v) input current ( a) bkbt biased at 3.6v v1, v2, and v3 on v1 and v2 on v1 on v1 and v2 sleep v1 sleep all but v7 off 200 160 40 60 80 120 0 100 50 200 150 250 300 0400 200 600 800 1000 1200 dropout voltage vs. load current MAX1586a/86b/87a toc08 load current (ma) dropout voltage (mv) reg1 3.3v output -100 0 -50 100 50 150 200 0 400 200 600 800 1000 1200 change in output voltage vs. load current MAX1586a/86b/87a toc09 load current (ma) change in output voltage (mv) v in = 3.6v reg1 3.3v output reg3 1.3v output reg2 2.5v output
MAX1586a/MAX1586b/max1587a high-efficiency, low-i q pmics with dynamic core for pdas and smart phones ______________________________________________________________________________________ 11 960 1000 880 920 1040 2.5 3.5 3.0 4.0 4.5 5.0 5.5 switching frequency vs. supply voltage MAX1586a/86b/87a toc10 input voltage (v) switching frequency (khz) t a = -40 c t a = +85 c t a = +25 c 1.225 1.265 1.260 1.255 1.250 1.245 1.240 1.235 1.230 -40 -15 10 35 60 85 reference voltage vs. temperature MAX1586a/86b/87a toc11 temperature ( c) reference voltage (v) reg1 switching waveforms with 800ma load MAX1586a/86b/87a toc12 400ns/div 0 0 500ma/div 10mv/div ac-coupled 2v/div v lx1 i l1 v1 reg1 switching waveforms with 10ma load MAX1586a/86b/87a toc13 20 s/div 0 0 500ma/div 50mv/div ac-coupled 2v/div v lx1 v1 i l1 reg3 switching waveforms with 250ma load MAX1586a/86b/87a toc14 400ns/div 0 0 500ma/div 10mv/div ac-coupled 2v/div v3 i l3 v lx3 reg3 pulse-skip switching waveforms with 10ma load MAX1586a/86b/87a toc15 10 s/div 0 0 500ma/div 10mv/div ac-coupled 2v/div v lx3 v3 i l3 t ypical operating characteristics (continued) (circuit of figure 5, v in = 3.6v, t a = +25 c, unless otherwise noted.)
MAX1586a/MAX1586b/max1587a high-efficiency, low-i q pmics with dynamic core for pdas and smart phones 12 ______________________________________________________________________________________ t ypical operating characteristics (continued) (circuit of figure 5, v in = 3.6v, t a = +25 c, unless otherwise noted.) pwr_en startup waveforms MAX1586a/86b/87a toc19 1ms/div 2v/div 2v/div 2v/div 2v/div 2v/div v5 v4 v3 v en3 and v en45 v pok reg1 load-transient response MAX1586a/86b/87a toc20 200 s/div 0a v1 100mv/div ac-coupled i load1 200ma/div reg2 load-transient response MAX1586a/86b/87a toc21 200 s/div 0a v2 100mv/div ac-coupled i load2 200ma/div reg3 forced-pwm switching waveforms with 10ma load MAX1586a/86b/87a toc16 400ns/div 0ma 0v 500ma/div 10mv/div ac-coupled 2v/div v lx3 v3 i l3 v7 and rso startup waveforms MAX1586a/86b/87a toc17 10ms/div 0v 2v/div 0v 2v/div 0v 2v/div rso v in v7 sys_en startup waveforms MAX1586a/86b/87a toc18 2ms/div 2v/div 2v/div 2v/div 2v/div v2 v1 v en1 and v en2 v pok
MAX1586a/MAX1586b/max1587a high-efficiency, low-i q pmics with dynamic core for pdas and smart phones ______________________________________________________________________________________ 13 t ypical operating characteristics (continued) (circuit of figure 5, v in = 3.6v, t a = +25 c, unless otherwise noted.) reg3 load-transient response MAX1586a/86b/87a toc22 200 s/div 0a v3 100mv/div ac-coupled i load3 200ma/div reg3 output voltage changing from 1.3v to 1.0v with different values of c ramp MAX1586a/86b/87a toc23 200 s/div c ramp = 2200pf c ramp = 1500pf c ramp = 1000pf c ramp = 330pf reg6 usim transitions MAX1586a/86b/87a toc24 10 s/div 0 500mv/div v6 2.5v to 3.0v v6 1.8v to 2.5v v6 0 to 1.8v
MAX1586a/MAX1586b/max1587a high-efficiency, low-i q pmics with dynamic core for pdas and smart phones 14 ______________________________________________________________________________________ pin description pin max 1586 max 1587 name function 1 lbi dual-mode, low-battery input. connect to in to set the low-battery threshold to 3.6v (no resistors needed). connect lbi to a resistor-divider for an adjustable lbi threshold. when in is below the set threshold, lbo output switches low. lbo is deactivated and forced low when in is below the dead-battery (dbi) threshold and when all regs are disabled. 2 40 cc1 reg1 compensation node. connect a series resistor and capacitor from cc1 to gnd to compensate the regulation loop. see the compensation and stability section . 31 fb1 reg1 feedback input. connect to in to set v1 to 3.0v or connect fb1 to gnd to set v1 to 3.3v. connect fb1 to external feedback resistors for other output voltages. 42 bkbt input connection for backup battery. this input can also accept the output of an external boost converter. 53v7 also known as vcc_batt. v7 is always active if main or backup power is present. it is the first regulator that powers up. v7 has two states: 1) v7 tracks v1 if on1 is high and v1 is in regulation. 2) v7 tracks v bkbt when on1 is low or v1 is out of regulation. 64v1 reg1 voltage-sense input. connect directly to the reg1 output voltage. the output voltage is set by fb1 to either 3.0v, 3.3v, or adjustable with resistors. 75 slpin inp ut to v 1 and v 2 s l eep reg ul ator s. th e i np ut to the stand b y r eg ul ator s at v 1 and v 2. c onnect s lp in to in . 86v2 reg2 voltage-sense input. connect directly to the reg2 output voltage. the output voltage is set by fb2 to either 1.8v/2.5v (MAX1586a, max1587a), 3.3v/2.5v (MAX1586b), or adjustable with resistors. 97 fb2 reg2 feedback input. connect to gnd to set v2 to 2.5v on all devices. connect fb2 to in to set v2 to 1.8v on the MAX1586a and max1587a. connect fb2 to in to set v2 to 3.3v on the MAX1586b. connect fb2 to external feedback resistors for other voltages. 10 8 cc2 reg2 compensation node. connect a series resistor and capacitor from cc2 to gnd to compensate the regulation loop. see the compensation and stability section. 11 9 pok power-ok output. open-drain output that is low when any of the v1?6 outputs are below their regulation threshold. when all activated outputs are in regulation, pok is high impedance. pok maintains a valid low output with v7 as low as 1v. pok does not flag an out-of-regulation condition while reg3 is transitioning between voltages set by serial programming. pok also does not flag for any reg channel that has been turned off; however, if all reg channels are off (v1?6), then pok is forced low. if in < uvlo, then pok is low. pok is expected to connect to nvcc_fault. 12 10 scl serial clock input 13 11 sda serial data input. data is read on the rising edge of scl. serial data programs the reg3 (core) and reg6 (vcc_usim) voltage. reg3 and reg6 can be programmed even when off, but at least one of the on_ pins must be logic-high to activate the serial interface. on power-up, reg3 defaults to 1.3v and reg6 defaults to 0v. 14 12 pwm3 force v3 to pwm at all loads. connect pwm3 to gnd for normal operation (skip mode at light loads). drive or connect high for forced-pwm operation at all loads for v3 only. 15 lbo low-battery output. open-drain output that goes low when in is below the threshold set by lbi. dual mode is a trademark of maxim integrated products, inc.
MAX1586a/MAX1586b/max1587a high-efficiency, low-i q pmics with dynamic core for pdas and smart phones ______________________________________________________________________________________ 15 pin description (continued) pin max 1586 max 1587 name function 16 13 pv2 reg2 power input. bypass to pg2 with a 4.7? or greater low-esr capacitor. pv1, pv2, pv3, and in must connect together externally. 17 14 lx2 reg2 switching node. connects to reg2 inductor. 18 15 pg2 reg2 power ground. connect directly to a power-ground plane. connect pg1, pg2, pg3, and gnd together at a single point as close to the ic as possible. 19 16 in main battery input. this input provides power to the ic. 20 17 ramp v3 ramp-rate control. a capacitor connected from ramp to gnd sets the rate-of-change when v3 is changed. the output impedance of ramp is 100k ? . fb3 regulates to 1.28 x v ramp . 21 18 gnd analog ground 22 19 ref reference output. output of the 1.25v reference. bypass to gnd with a 0.1? or greater capacitor. 23 20 byp low-noise ldo bypass. low-noise bypass pin for v4 ldo. connect a 0.01? capacitor from byp to gnd. 24 dbo dead or missing battery output. dbo is an open-drain output that goes low when in is below the threshold set by dbi. dbo does not deactivate any MAX1586/max1587 regulator outputs. dbo is expected to connect to nbatt_fault on intel cpus. 25 21 on2 on/off input for reg2. drive high to turn on. when enabled, the reg2 output soft-starts. on2 has hysteresis so an rc can be used to implement manual sequencing with respect to other inputs. it is expected that on1, on2, and on6 are connected to sys_en. 26 on4 on/off input for reg4. drive high to turn on. when enabled, the reg4 output activates. on4 has hysteresis so an rc can be used to implement manual sequencing with respect to other inputs. it is expected that on4 is connected to pwr_en. 27 23 v4 also known as vcc_pll. 1.3v, 35ma linear-regulator output for pll. regulator input is in45. 28 24 in45 power input to v4 and v5 ldos. typically connected to v2, but can also connect to in or another voltage from 2.5v to v in . 29 25 v5 also known as vcc_sram. 1.1v, 35ma linear-regulator output for cpu sram. regulator input is in45. 30 on5 on/off input for reg5. drive high to turn on. when enabled, the MAX1586/max1587 soft-starts the reg5 output. on5 has hysteresis so an rc can be used to implement manual sequencing with respect to other inputs. it is expected that on5 is connected to pwr_en. 31 26 pg3 reg3 power ground. connect directly to a power-ground plane. connect pg1, pg2, pg3, and gnd together at a single point as close to the ic as possible. 32 27 lx3 reg3 switching node. connects to the reg3 inductor. 33 28 pv3 reg3 power input. bypass to pg3 with a 4.7? or greater low-esr ceramic capacitor. pv1, pv2, pv3, and in must connect together externally. 34 34 on3 on/off input for reg3 (core). drive high to turn on. when enabled, the reg3 output ramps up. on3 has hysteresis so an rc can be used to implement manual sequencing with respect to other inputs. it is expected that on3 is driven from cpu sys_en.
MAX1586a/MAX1586b/max1587a high-efficiency, low-i q pmics with dynamic core for pdas and smart phones 16 ______________________________________________________________________________________ pin description (continued) pin max 1586 max 1587 name function 35 29 srad serial address bit. srad allows the serial address of the MAX1586/max1587 to be changed in case it conflicts with another serial device. if srad = gnd, a1 = 0. if srad = in, a1 = 1. 36 30 rso open-drain reset output. deasserts when v7 exceeds 2.55v (typ rising). has 65ms delay before release. rso is expected to connect to nreset on the cpu. 37 31 mr manual reset input. a low input causes the rso output to go low but impacts no other MAX1586/max1587 functions. 38 32 cc3 reg 3 compensation node. connect a series resistor and capacitor from cc3 to gnd to compensate the regulation loop. see the compensation and stability section . 39 33 fb3 reg3 feedback-sense input. connect directly to the reg3 output voltage. output voltage is set by the serial interface. 40 on6 on/off input for reg6. drive high to turn on. when enabled, the reg6 output activates. on6 has hysteresis so an rc can be used to implement manual sequencing with respect to other inputs. it is expected that on1, on2, and on6 are connected to sys_en. 41 v6 also known as vcc_usim. linear-regulator output. this voltage is programmable through the i 2 c interface to 0v, 1.8v, 2.5v, or 3.0v. the default voltage is 0v. reg6 is activated when on6 is high. 42 in6 power input to the v6 ldo. typically connected to v1, but can also connect to in. 43 36 pg1 reg1 power ground. connect directly to a power-ground plane. connect pg1, pg2, pg3, and gnd together at a single point as close to the ic as possible. 44 37 lx1 reg1 switching node. connects to the reg1 inductor. 45 38 pv1 reg1 power input. bypass to pg2 with a 4.7? or greater low-esr ceramic capacitor. pv1, pv2, pv3, and in must connect together externally. 46 35 on1 on/off input for reg1. drive high to turn on reg1. when enabled, the reg1 output soft-starts. on1 has hysteresis so an rc can be used to implement manual sequencing with respect to other inputs. it is expected that on1, on2, and on6 connect to sys_en. 47 39 slp sleep input. slp selects which regulators on1 and on2 turn on. slp = high is normal operation (on1 and on2 are the enables for the v1 and v2 dc-dc converters). slp = low is sleep operation (on1 and on2 are the enables for the v1 and v2 ldos). 48 dbi dual-mode, dead-battery input. connect dbi to in to set the dead-battery falling threshold to 3.15v (no resistors needed). connect dbi to a resistor-divider for an adjustable dbi threshold. ? 2 on45 on/off input for reg4 and reg5. drive high to turn on. when enabled, the reg4 and reg5 outputs activate. on45 has hysteresis so an rc can be used to implement manual sequencing with respect to other inputs. it is expected that on45 is connected to pwr_en. ep ep ep exposed metal pad. connect the exposed pad to ground. connecting the exposed pad to ground does not remove the requirement for proper ground connections to the appropriate ground pins. purchase of i 2 c components of maxim integrated products, inc. or one of its sublicensed associated companies, conveys a license under the phillips i 2 c patent rights to use these com- ponents in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by phillips.
MAX1586a/MAX1586b/max1587a high-efficiency, low-i q pmics with dynamic core for pdas and smart phones ______________________________________________________________________________________ 17 main batt pv1 batt step-down pwm reg1 sleep ldo lx1 pg1 v1 fb1 v2 fb2 pv2 on slpin in on step-down pwm reg2 sleep ldo lx2 pg2 fb3 on3 in45 v4 byp on4 on5 v6 on6 in6 v5 pv3 to batt to v2 to v2 to batt pwm ldo reg 4 ldo reg 5 step-down pwm reg3 lx3 pg3 ldo reg 6 v2, vcc_mem 2.5v with fb2 = gnd, 1.8v with fb2 = in (MAX1586a, max1587a) 3.3v with fb2 = in (MAX1586b) or adj with resistors v1, vcc_io 3.3v with fb1 = gnd, 3.0v with fb1 = in, or adj with resistors vcc_usim 0v, 1.8v, 3.0v (def = 0v) v4, vcc_pll 1.3v, 35ma v5, vcc_sram 1.1v, 35ma v3, vcc_core 0.75v to 1.3v (def = 1.3v) from cpu pwr_en from cpu sys_en on1 run sleep on2 dbi (3.15v or adj) lbo ref 1.25v ref uvlo and batt mon lbi (3.6v or adj) bkbt dbo slp to v1 reg1 ok pok scl sda gnd i 2 c serial cc1 v7, vcc_batt (1st supply, always on) from cpu sys_en v7 v1?6 power- ok cc2 cc3 to cpu nreset to cpu nvcc_fault rso mr reset input li+ backup battery open-drain low-batt out open-drain dead-batt out to nbatt_fault v3 dac ramp srad pwm3 force reg3 to pwm v7 reset 2.425v 65ms adj on MAX1586 100k ? figure 1. MAX1586 functional diagram. the max1587 omits some features. see the pin description section.
MAX1586a/MAX1586b/max1587a high-efficiency, low-i q pmics with dynamic core for pdas and smart phones 18 ______________________________________________________________________________________ detailed description the MAX1586/max1587 power-management ics are optimized for devices using intel x-scale microproces- sors, including third-generation smart cell phones, pdas, internet appliances, and other portable devices requiring substantial computing and multimedia capability at low power. the MAX1586a/MAX1586b/ max1587a comply with intel processor power specifications. the ics integrate seven high-performance, low-operat- ing-current power supplies along with supervisory and management functions. regulator outputs include three step-down dc-dc outputs (v1, v2, and v3), three lin- ear regulators (v4, v5, and v6), and one always-on out- put, v7 (intel vcc_batt). the v1 step-down dc-dc converter provides 3.0v, 3.3v, or adjustable output volt- age for i/o and peripherals. the v2 step-down dc-dc converter on the MAX1586a and max1587a is preset for 1.8v or 2.5v, while the MAX1586b v2 supply is pre- set for 3.3v or 2.5v. v2 can also be adjusted with exter- nal resistors on all parts. the v3 step-down dc-dc converter provides a serial-programmed output for powering microprocessor cores. the three linear regu- lators (v4, v5, and v6) provide power for pll, sram, and usim. to minimize sleep-state quiescent current, v1 and v2 have bypass ?leep?ldos that can be activated to minimize battery drain when output current is very low. other functions include separate on/off control for all dc-dc converters, low-battery and dead-battery detection, a power-ok output, a backup-battery input, and a two-wire serial interface. all dc-dc outputs use fast, 1mhz pwm switching and small external components. they operate with fixed-fre- quency pwm control and automatically switch from pwm to skip-mode operation at light loads to reduce operating current and extend battery life. the v3 core output is capable of forced-pwm operation at all loads. the 2.6v to 5.5v input voltage range allows 1-cell li+, 3-cell nimh, or a regulated 5v input. the following power-supply descriptions include the intel terms for the various voltages in parenthesis. for example, the MAX1586/max1587 v1 output is referred to as vcc_io in intel documentation. see figure 1. v1 and v2 (vcc_io, vcc_mem) step-down dc-dc converters v1 is a 1mhz current-mode step-down converter. the v1 output voltage can be preset to 3.3v or adjusted using a resistor voltage-divider. v1 supplies loads up to 1300ma. v2 is also a 1mhz current-mode step-down converter. the v2 step-down dc-dc converter on the MAX1586a and max1587a is preset for 1.8v or 2.5v, while the MAX1586b v2 supply is preset for 3.3v or 2.5v. v2 can also be adjusted with external resistors on all parts. v2 supplies loads up to 900ma. under moderate to heavy loading, the converters operate in a low-noise pwm mode with constant frequency and modulated pulse width. switching harmonics generated by fixed-frequency operation are consistent and easily fil- tered. efficiency is enhanced under light loading (<30ma typ), by assuming an idle mode ? during which the con- verter switches only as needed to service the load. synchronous rectification internal n-channel synchronous rectifiers eliminate the need for external schottky diodes and improve efficien- cy. the synchronous rectifier turns on during the sec- ond half of each cycle (off-time). during this time, the voltage across the inductor is reversed, and the induc- tor current falls. in normal operation (not forced pwm), the synchronous rectifier turns off at the end of the cycle (at which time another on-time begins) or when the inductor current approaches zero. 100% duty-cycle operation if the inductor current does not rise sufficiently to sup- ply the load during the on-time, the switch remains on, allowing operation up to 100% duty cycle. this allows the output voltage to maintain regulation while the input voltage approaches the regulation voltage. dropout voltage is approximately 180mv for an 800ma load on v1 and 220mv for an 800ma load on v2. during dropout, the high-side p-channel mosfet turns on, and the controller enters a low-current-consumption mode. the device remains in this mode until the regula- tor channel is no longer in dropout. sleep ldos in addition to the high-efficiency step-down converters, v1 and v2 can also be supplied with low-quiescent cur- rent, low-dropout (ldo) linear regulators that can be used in sleep mode or at any time when the load current is very low. the sleep ldos can source up to 35ma. to idle mode is a trademark of maxim integrated products, inc.
MAX1586a/MAX1586b/max1587a high-efficiency, low-i q pmics with dynamic core for pdas and smart phones ______________________________________________________________________________________ 19 enable the sleep ldos, drive slp low. when slp is high, the switching step-down converters are active. the output voltage of the sleep ldos is set to be the same as the switching step-down converters as described in the setting the output voltages section. slpin is the input to the v1 and v2 sleep ldos and must connect to in. v3 (vcc_core) step-down dc-dc converter v3 is a 1mhz current-mode step-down converter that supplies loads up to 500ma. the v3 output voltage is set by the i 2 c serial interface to between 0.7v and 1.475v in 25mv increments. the default voltage on power-up is 1.3v. see the serial interface section for details. forced pwm on reg3 under moderate to heavy loading, the v3 always operates in a low-noise pwm mode with constant frequency and modulated pulse width. switching harmonics generated by fixed-frequency operation are consistent and easily filtered. with light loads (<30ma) and pwm3 low, v3 operates in an enhanced-efficiency idle mode during which the converter switches only as needed to service the load. with pwm3 high, v3 operates in low-noise forced-pwm mode under all load conditions. linear regulators (v4, v5, and v6) v4 (vcc_pll) v4 is a linear regulator that provides a fixed 1.3v output and supplies loads up to 35ma. the power input for the v4 and v5 linear regulators is in45, which is typically connected to v2. to enable v4 on the max1587, drive on4 high, or drive on4 low for shutdown. on the MAX1586, the enable pins for v4 and v5 are combined. drive on45 high to enable v4 and v5, or drive on45 low for shutdown. v4 is intended to connect to vcc_pll. v5 (vcc_sram) v5 is a linear regulator that provides a fixed 1.1v output and supplies loads up to 35ma. the power input for the v4 and v5 linear regulators is in45, which is typically connected to v2. to enable v5 on the max1587, drive on5 high, or drive on5 low for shutdown. on the MAX1586, the enable pins for v4 and v5 are combined. drive on45 high to enable v4 and v5, or drive on45 low for shutdown. v5 is intended to connect to vcc_sram. v6 (vcc_usim?ax1586 only) v6 is a linear regulator on the MAX1586 that supplies loads up to 35ma. the v6 output voltage is pro- grammed with the i 2 c serial interface to 0v, 1.8v, 2.5v, or 3.0v. the power-up default for v6 is 0v. see the serial interface section for details on changing the volt- age. the power input for the v6 linear regulator is in6, which is typically connected to v1. to enable v6, drive on6 high, or drive on6 low for shutdown. v6 is intend- ed to connect to vcc_usim. v7 always-on output (vcc_batt) the v7 output is always active if v1 is enabled and in regulation or if backup power is present. when on1 is high and v1 is in regulation, v7 is sourced from v1 by an internal mosfet switch. when on1 is low or v1 is table 1. quiescent operating current in various states operating power mode description typical MAX1586/max1587 no-load operating current run all supplies on and running idle all supplies on and running, peripherals on sense all supplies on, minimal loading, peripherals monitored standby all supplies on, minimal loading, peripherals not monitored 200? max1587, 225? MAX1586 sleep p w r_e n contr ol l ed vol tag es ( v 3, v 4, v 5) ar e off. v 1 and v 2 on. 60? if v1 and v2 sleep ldos on; 130? if v1, v2 step-down dc-dcs enabled deep sleep all supplies off except v7. v7 biased from backup battery. 5? max1587 if in > dbi threshold; 32? MAX1586 if in > dbi threshold; 4? if in < dbi threshold
MAX1586a/MAX1586b/max1587a high-efficiency, low-i q pmics with dynamic core for pdas and smart phones 20 ______________________________________________________________________________________ out of regulation, v7 is sourced from bkbt by a second on-chip mosfet. v7 can supply loads up to 30ma. v7 is intended to connect to vcc_batt on intel cpus. due to variations in system implementation, bkbt and v7 can be utilized in different ways. see the backup- battery configurations section for information on how to use bkbt and v7. quiescent operating current in various states the MAX1586/max1587 are designed for optimum effi- ciency and minimum operating current for all typical operating modes, including sleep and deep sleep. these states are outlined in table 1. voltage monitors, reset, and undervoltage-lockout functions undervoltage lockout when the input voltage is below 2.35v (typ), an under- voltage-lockout (uvlo) circuit disables the ic. the inputs remain high impedance while in uvlo, reducing battery load under this condition. all serial registers are maintained with the input voltage down to at least 2.35v. reset output (rso) and mr input the reset output ( rso ) is low when the mr input is low or when v7 is below 2.425v. v7 is powered from v1 (when enabled) or the backup-battery input (bkbt). rso normally goes low: 1) when power is first applied in configurations with no separate backup battery (external diode from in to bkbt). 2) when power is removed in configurations with no separate backup battery (external diode from in to bkbt). 3) if the backup battery falls below 2.425v when v1 is off or out of regulation. 4) when the manual reset button is pressed ( mr goes low). rso has a timer that delays release until 65ms after v7 exceeds 2.3v when v in > 2.4v. if v in < 2.4v when v7 exceeds 2.3v, rso deasserts immediately with no 65ms delay. there is no delay in this case because the timer circuitry is deactivated to minimize operating current dur- ing in undervoltage lockout. rso is not triggered by any output besides v7. if bkbt is not powered, rso does not function and is high impedance. mr is a manual reset input for hardware reset. when mr goes low, rso asserts for a minimum of 65ms. mr does not reset any internal MAX1586/max1587 functions. dead-battery and low-battery comparators dbi, lbi (MAX1586 only) the dbi and lbi inputs monitor input power (usually a battery) and trigger the dbo and lbo outputs. the dead-battery comparator triggers dbo when the battery (v in ) discharges to the dead-battery threshold. the factory-set 3.15v threshold is selected by connecting dbi to in, or the threshold can be programmed with a resistor-divider at dbi. the low-battery comparator has a factory-set 3.6v threshold that is selected by connect- ing lbi to in, or its threshold can be programmed with a resistor-divider at lbi. one three-resistor-divider can set both dbi and lbi (r1, r2, and r3 in figure 2) according to the following equations: 1) choose r3 to be less than 250k ? 2) r1 = r3 v lb (1 - (1.232 / v db )) 3) r2 = r3 (1.232 x (v lb / v db ) - 1) where v lb is the low-battery threshold and v db is the dead-battery threshold. alternately, lbi and dbi can be set with separate two- resistor-dividers. choose the lower resistor of the divider chain to be 250k ? or less (r5 and r7 in figure 3). the equations for upper divider-resistors as a function of each threshold are then: r4 = r5 (v db / 1.232) - 1) r6 = r7 (v lb - 1) when resistors are used to set v lb , the threshold at lbi is 1.00v. when resistors are used to set v db , the threshold at dbi is 1.232v. a resistor-set threshold can MAX1586 main battery r1 438k ? r2 62k ? r3 200k ? in dbi (1.232v threshold) lbi (1.00v threshold) figure 2. setting the low-battery and dead-battery thresholds with one resistor chain. the values shown set a dbi threshold of 3.3v and an lbi threshold of 3.5v (no resistors are needed for the factory preset thresholds).
MAX1586a/MAX1586b/max1587a high-efficiency, low-i q pmics with dynamic core for pdas and smart phones ______________________________________________________________________________________ 21 also be used for only one of dbi or lbi. the other threshold can then be factory set by connecting the appropriate input to in. if bkbt is not powered, dbo does not function and is high impedance. dbo is expected to connect to nbatt_fault on intel cpus. if bkbt is not powered, lbo does not function and is high impedance. power-ok output (pok) pok is an open-drain output that goes low when any activated regulator (v1?6) is below its regulation threshold. pok does not monitor v7. when all active output voltages are within 10% of regulation, pok is high impedance. pok does not flag an out-of-regula- tion condition while v3 is transitioning between voltages set by serial programming or when any regulator chan- nel has been turned off. pok momentarily goes low when any regulator is turned on, but returns high when that regulator reaches regulation. when all regulators (v1?6) are off, pok is forced low. if the input voltage is below the uvlo threshold, pok is held low and maintains a valid low output with in as low as 1v. if bkbt is not powered, pok does not function and is high impedance. connection to processor and power sequencing typical processor connections have only power-control pins, typically labeled pwr_en and sys_en. the MAX1586/max1587 provide numerous on/off control pins for maximum flexibility. in a typical application, many of these pins are connected together. on1, on2, and on6 typically connect to sys_en. on3, on4, and on5 typically connect to pwr_en. v7 remains on as long as the main or backup power is connected. sequencing is not performed internally on the MAX1586/max1587; however, all on_ inputs have hysteresis and can connect to rc networks to set sequencing. for typical connec- tions to intel cpus, no external sequencing is required. backup-battery input the backup-battery input (bkbt) provides backup power for v7 when v1 is disabled. normally, a primary or rechargeable backup battery is connected to this pin. if a backup battery is not used, then bkbt should connect to in through a diode or external regulator. see the backup-battery configurations section for informa- tion on how to use bkbt and v7. serial interface an i 2 c-compatible, two-wire serial interface controls reg3 on the max1587, and reg3 and reg6 on the MAX1586. the serial interface operates when in exceeds the 2.40v uvlo threshold and at least one of on1?n6 is asserted. the serial interface is shut down to minimize off-current drain when no regulators are enabled. the serial interface consists of a serial data line (sda) and a serial clock line (scl). standard i 2 c-compatible write-byte commands are used. figure 4 shows a tim- ing diagram for the i 2 c protocol. the MAX1586/ max1587 are slave-only devices, relying upon a master to generate a clock signal. the master (typically a microprocessor) initiates data transfer on the bus and generates scl to permit data transfer. a master device communicates to the MAX1586/max1587 by transmit- ting the proper address followed by the 8-bit data code (table 2). each transmit sequence is framed by a start (a) condition and a stop (l) condition. each word transmitted over the bus is 8 bits long and is always followed by an acknowledge clock pulse. table 2 shows the serial data codes used to program v3 and v6. the default power-up voltage for v3 is 1.3v and for v6 is 0v. MAX1586 main battery r6 500k ? r7 200k ? in dbi (1.232v threshold) lbi (1.00v threshold) r5 200k ? r4 334k ? figure 3. setting the low-battery and dead-battery thresholds with separate resistor-dividers. the values shown set a dbi threshold of 3.3v and an lbi threshold of 3.5v (no resistors are needed for factory-preset thresholds).
MAX1586a/MAX1586b/max1587a high-efficiency, low-i q pmics with dynamic core for pdas and smart phones 22 ______________________________________________________________________________________ bit transfer one data bit is transferred during each scl clock cycle. the data on sda must remain stable during the high period of the scl clock pulse. changes in sda while scl is high are control signals (see the start and stop conditions section). both sda and scl idle high when the bus is not busy. start and stop conditions when the serial interface is inactive, sda and scl idle high. a master device initiates communication by issu- ing a start condition. a start condition is a high-to- low transition on sda with scl high. a stop condition is a low-to-high transition on sda while scl is high (figure 4). a start condition from the master signals the beginning of a transmission to the MAX1586/ max1587. the master terminates transmission by issu- ing a not acknowledge followed by a stop condition (see the acknowledge bit section). the stop condition frees the bus. when a stop condition or incorrect address is detect- ed, the MAX1586/max1587 internally disconnect scl from the serial interface until the next start condition, minimizing digital noise and feedthrough. acknowledge bit (ack) the acknowledge bit (ack) is the ninth bit attached to every 8-bit data word. the receiving device always generates ack. the MAX1586/max1587 generate an ack when receiving an address or data by pulling sda low during the ninth clock period. monitoring ack allows for detection of unsuccessful data transfers. an unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. in the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time. serial address a bus master initiates communication with a slave device by issuing a start condition followed by the 7-bit slave address (table 3). when idle, the MAX1586/max1587 wait for a start condition fol- lowed by its slave address. the serial interface com- pares each address value bit by bit, allowing the interface to power down immediately if an incorrect address is detected. the lsb of the address word is the read/write (r/ w ) bit. r/ w indicates whether the master is writing or reading (rd/ w 0 = write, rd/ w 1 = read). the MAX1586/ max1587 only support the send byte format; there- fore, rd/ w is required to be 0. after receiving the proper address, the MAX1586/ max1587 issue an ack by pulling sda low for one clock cycle. the MAX1586/max1587 have two user- programmed addresses (table 3). address bits a6 through a1 are fixed, while a1 is controlled by srad. connecting srad to gnd sets a1 = 0. connecting add to in sets a1 = 1. v3 output ramp-rate control when v3 is dynamically changed with the serial inter- face, the output voltage changes at a rate controlled by a capacitor (c ramp ) connected from ramp to ground. scl ab cdefg hijk sda t su:sta t hd:sta t low t high t su:dat t hd:dat t su:sto t buf a = start condition b = msb of address clocked into slave c = lsb of address clocked into slave d = r/w bit clocked into slave e = slave pulls smb data line low l m f = acknowledge bit clocked into master g = msb of data clocked into slave (op/sus bit) h = lsb of data clocked into slave i = slave pulls smb data line low j = acknowledge clocked into master k = acknowledge clock pulse l = stop condition, data executed by slave m = new start condition figure 4. i 2 c-compatible serial-interface timing diagram
MAX1586a/MAX1586b/max1587a high-efficiency, low-i q pmics with dynamic core for pdas and smart phones ______________________________________________________________________________________ 23 table 2. v3 and v6 serial programming codes d7 d6 d5 0 = prog v3 1 = prog v6 d4 d3 d2 d1 d0 output (v) description 0 00000 0.700 0 00001 0.725 0 00010 0.750 0 00011 0.775 0 00100 0.800 0 00101 0.825 0 00110 0.850 0 00111 0.875 0 01000 0.900 0 01001 0.925 0 01010 0.950 0 01011 0.975 0 01100 1.000 0 01101 1.025 0 01110 1.050 0 01111 1.075 0 10000 1.100 0 10001 1.125 0 10010 1.150 0 10011 1.175 0 10100 1.200 0 10101 1.225 0 10110 1.250 0 10111 1.275 0 11000 1.300 0 11001 1.325 0 11010 1.350 0 11011 1.375 0 11100 1.400 0 11101 1.425 0 11110 1.450 0 11111 1.475 v3, core voltages 1 xxx0 0 0 1 xxx011.8 1 xxx102.5 xx 1 xxx113.0 v6, usim voltages [MAX1586 only]
MAX1586a/MAX1586b/max1587a high-efficiency, low-i q pmics with dynamic core for pdas and smart phones 24 ______________________________________________________________________________________ the voltage change is a conventional rc exponential described by: vo(t) = vo(0) + dv(1 ?exp(-t / (100k ? c ramp ))) a useful approximation is that it takes approximately 2.2 rc time constants for v3 to move from 10% to 90% of the voltage difference. for c ramp = 1500pf, this time is 330?. for 1v to 1.3v change, this equates to 1mv/?. see the typical operating characteristics for examples of different ramp-rate settings. the maximum capacitor value that can be used at ramp is 2200pf. if larger values are used, the v3 ramp rate is still controlled according to the above equation, but when v3 is first activated, pok indicates an ?n reg- ulation?condition before v3 reaches its final voltage. the ramp pin is effectively the reference for reg3. fb3 regulates to 1.28 times the voltage on ramp. design procedure setting the output voltages the outputs v1 and v2 have preset output voltages, but can also be adjusted using a resistor voltage-divider. v1 has 3.3v and 3.0v presets. to set v1 to 3.0v, connect fb1 to in. to set to 3.3v, connect fb1 to gnd. v2 can be preset to 1.8v or 2.5v on the MAX1586a and max1587a. to set v2 to 1.8v on the MAX1586a and max1587a, connect fb2 to in. to set to 2.5v, connect fb2 to gnd. v2 can preset to 3.3v or 2.5v on the max1587b. to set v2 to 3.3v on the max1587b, connect fb2 to in. to set to 2.5v, connect fb2 to gnd. to set v1 or v2 to other than the preset output voltages, connect a resistor voltage-divider from the output volt- age to the corresponding fb input. the fb_ input bias current is less than 100na, so choose the low-side (fb_- to-gnd) resistor (r l ) to be 100k ? or less. then calcu- late the high-side (output-to-fb_) resistor (r h ) using: r h = r l [(v out / 1.25) ?1] the v3 (vcc_core) output voltage is set from 0.7v to 1.475v in 25mv steps by the i 2 c serial interface. see the serial interface section for details. linear regulator v4 provides a fixed 1.3v output volt- age. linear regulator v5 provides a fixed 1.1v output voltage. v4 and v5 voltages are not adjustable. the output voltage of linear regulator v6 (vcc_usim) is set to 0v, 1.8v, 2.5v, or 3.0v by the i 2 c serial interface. see the serial interface section for details. linear regulator v7 (vcc_batt) tracks the voltage at v1 as long as on1 is high and v1 is in regulation. when on1 is low or v1 is not in regulation, v7 switches to the backup battery (v bkbt ). inductor selection the external components required for the step-down are an inductor, input and output filter capacitors, and a compensation rc network. the MAX1586/max1587 step-down converters provide best efficiency with continuous inductor current. a rea- sonable inductor value (l ideal ) is derived from: l ideal = [2(v in ) x d(1 - d)] / (i out(max) x f osc ) this sets the peak-to-peak inductor current at 1/2 the dc inductor current. d is the duty cycle: d = v out / v in given l ideal , the peak-to-peak inductor ripple current is 0.5 x i out . the peak inductor current is 1.25 x i out(max) . make sure the saturation current of the inductor exceeds the peak inductor current and the rated maximum dc inductor current exceeds the maxi- mum output current (i out(max) ). inductance values larger than l ideal can be used to optimize efficiency or to obtain the maximum possible output current. larger inductance values accomplish this by supplying a given load current with a lower inductor peak current. typically, output current and efficiency are improved for inductor values up to about two times l ideal . if the inductance is raised too much, however, the inductor size may become too large, or the increased inductor resistance may reduce efficiency more than the gain derived from lower peak current. smaller inductance values allow smaller inductor sizes, but also result in larger peak inductor current for a given load. larger output capacitance may then be needed to suppress the increase in output ripple caused by larger peak current. capacitor selection the input capacitor in a dc-dc converter reduces cur- rent peaks drawn from the battery or other input power source and reduces switching noise in the controller. the impedance of the input capacitor at the switching frequency should be less than that of the input source so high-frequency switching currents do not pass through the input source. the output capacitor keeps output ripple small and ensures control-loop stability. the output capacitor table 3. serial address srad a7 a6 a5 a4 a3 a2 a1 a0 rd/w 0 0010100 0 1 0010101 0
MAX1586a/MAX1586b/max1587a high-efficiency, low-i q pmics with dynamic core for pdas and smart phones ______________________________________________________________________________________ 25 must also have low impedance at the switching fre- quency. ceramic, polymer, and tantalum capacitors are suitable, with ceramic exhibiting the lowest esr and lowest high-frequency impedance. output ripple with a ceramic output capacitor is approximately: v ripple = i l(peak) [1 / (2 x f osc x c out )] if the capacitor has significant esr, the output ripple component due to capacitor esr is: v ripple(esr) = i l(peak) x esr output capacitor specifics are also discussed in the compensation and stability section. compensation and stability the relevant characteristics for reg1, reg2, and reg3 compensation are: 1) transconductance (from fb_ to cc_), gm ea 2) current-sense amplifier transresistance, r cs 3) feedback regulation voltage, v fb (1.25v) 4) step-down output voltage, v out , in v 5) output load equivalent resistance, r load = v out / i load the key steps for step-down compensation are: 1) set the compensation rc zero to cancel the r load c out pole. 2) set the loop crossover at or below approximately 1/10th the switching frequency. for example, with v in(max) = 5v, v out = 2.5v for reg2, and i out = 800ma, then r load = 3.125 ? . for reg2, r cs = 0.75v/a and gm ea = 87?. choose the crossover frequency, f c f osc / 10. choose 100khz. then calculate the value of the com- pensation capacitor, c c : c c = (v fb / v out ) x (r load / r cs ) x (gm / (2 x f c )) = (1.25 / 2.5) x (3.125 / 0.75) x (87 x 10 -6 / (6.28 x 100,000)) = 289pf choose 330pf, the next highest standard value. now select the compensation resistor, r c , so transient- droop requirements are met. as an example, if 3% tran- sient droop is allowed for the desired load step, the input to the error amplifier moves 0.03 x 1.25v, or 37.5mv. the error-amplifier output drives 37.5mv x gm ea , or i eao = 37.5mv x 87? = 3.26? across r c to provide transient gain. find the value of r c that allows the required load-step swing from: r c = r cs x i ind(pk) / i eao where i ind(pk) is the peak inductor current. in a step- down dc-dc converter, if l ideal is used, output cur- rent relates to inductor current by: i ind(pk) = 1.25 x i out so for an 800ma output load step with v in = 3.6v and v out = 2.5v: r c = r cs x i ind(pk) / i eao = (0.75v/a) x (1.25 x 0.8a) / 3.26? = 230k ? we choose 240k ? . note that the inductor does not limit the response in this case since it can ramp at (v in - v out ) / l, or (3.6 - 2.5) / 3.3? = 242ma/?. the output filter capacitor is then selected so that the c out r load pole cancels the r c c c zero: c out x r load = r c x c c for the example: r load = v out x i load = 2.5v / 0.8a = 3.125 ? c out = r c x c c / r load = 240k ? x 330pf / 3.125 ? = 25? we choose 22?. recalculate r c using the selected c out . r c = c out x r load / c c = 208k ? parameter reg1 reg2 reg3 error-amplifier transconductance, gm ea 87? 87? 68? current-sense amp transresistance, r cs 0.5v/a 0.75v/a 1.25v/a table 4. compensation parameters component or parameter reg1 reg2 reg3 v out 3.3v 2.5v 1.3v output current 1300ma 900ma 500ma inductor 3.3? 6.8? 10? load-step droop 3% 3% 3% loop crossover freq (f c ) 100khz 100khz 100khz c c 330pf 270pf 330pf r c 240k ? 240k ? 240k ? c out 22? 22? 22? table 5. typical compensation values
MAX1586a/MAX1586b/max1587a high-efficiency, low-i q pmics with dynamic core for pdas and smart phones 26 ______________________________________________________________________________________ main batt pv1 batt to batt step-down pwm reg1 sleep ldo lx1 c12 4.7 f c11 10 f c19 0.1 f c25 1 f c24 1 f c28 330pf c27 270pf c26 330pf r20 1m ? r21 240k ? r18 1m ? r22 240k ? r23 240k ? r19 1m ? c15 22 f c16 22 f c17 22 f c13 4.7 f c14 4.7 f c20 0.01 f c23 1 f c22 1 f c21 1 f l1 3.3 h l2 6.8 h l3 10 h pg1 v1 fb1 v2 fb2 pv2 on slpin in on step-down pwm reg2 sleep ldo lx2 pg2 fb3 on3 in45 v4 byp on4 on5 in6 on6 v5 v6 pv3 to batt to v2 to v2 to batt pwm ldo reg 4 ldo reg 5 step-down pwm reg3 lx3 pg3 ldo reg 6 v1 vcc_io 3.3v 1300ma v2 vcc_mem 2.5v 900ma v6 vcc_usim 0v, 1.8v, 3.0v (def = 0v) 35ma v4, vcc_pll 1.3v, 35ma v5 vcc_sram 1.1v, 35ma v3 vcc_core 0.75v to 1.3v 500ma from cpu pwr_en from cpu sys_en on1 run sleep on2 dbi (3.2v or adj) lbo ref 1.25v ref uvlo and batt mon lbi (3.6v or adj) bkbt dbo slp to v1 to v1 to v1 reg1 ok pok adj on scl sda gnd i 2 c serial cc1 v7, vcc_batt (always on) from cpu sys_en v7 v1?6 power- ok cc2 cc3 to cpu nreset to cpu nvcc-fault rso mr reset input li+ backup battery low-batt warning to cpu nbatt_fault v3 dac ramp c18 1500pf srad pwm3 v7 reset 2.3v 65ms MAX1586 100k ? figure 5. MAX1586 typical applications circuit. the max1587 omits some features. see the pin description section.
MAX1586a/MAX1586b/max1587a high-efficiency, low-i q pmics with dynamic core for pdas and smart phones ______________________________________________________________________________________ 27 note that the pole cancellation does not have to be exact. r c x c c need only be within 0.75 to 1.25 times r load x c out . this provides flexibility in component selection. if the output filter capacitor has significant esr, a zero occurs at: z esr = 1 / (2 x c out x r esr ) if z esr > f c , it can be ignored, as is typically the case with ceramic or polymer output capacitors. if z esr is less than f c , it should be cancelled with a pole set by capacitor c p connected from cc_ to gnd: c p = c out r esr / r c if c p is calculated to be < 10pf, it can be omitted. optimizing transient response in applications that require load-transient response to be optimized in favor of minimum component values, increase the output filter capacitor to increase the r in the compensation rc. from the equations in the previ- ous section, doubling the output cap allows a doubling of the compensation r, which then doubles the tran- sient gain. applications information backup-battery and v7 configurations the MAX1586/max1587 include a backup-battery con- nection, bkbt, and an output, v7. these can be utilized in different ways for various system configurations. primary backup battery a connection with a primary (nonrechargeable) lithium coin cell is shown in figure 5. the lithium cell connects to bkbt directly. v7 powers the cpu vcc_batt from either v1 (if enabled) or the backup battery. it is assumed whenever the main battery is good, v1 is on (either with its dc-dc converter or sleep ldo) to supply v7. no backup battery (or alternate backup) if no backup battery is used, or if an alternate backup and vcc_batt scheme is used that does not use the MAX1586/max1587, then bkbt should be biased from in with a small silicon diode (1n4148 or similar, as in figure 6). bkbt must still be powered when no backup battery is used because dbo , rso , and pok require this supply to function. if bkbt is not powered, these outputs do not function and are high impedance. rechargeable li+ backup battery if more backup power is needed and a primary cell has inadequate capacity, a rechargeable lithium cell can be accommodated as shown in figure 7. a series resistor and diode charge the cell when the 3.3v v1 supply is MAX1586 max1587 main power d1 1n4148 in bkbt v7 4.7 f 1 f figure 6. bkbt connection when no backup battery is used, or if an alternate backup scheme, not involving the MAX1586/max1587, is used. MAX1586 max1587 main power 1-cell li+ rechargeable backup battery in bkbt 1k ? v7 v1 4.7 f 1 f 4.7 f figure 7. a 1-cell rechargeable li+ battery provides more back- up power when a primary cell is insufficient. the cell is charged to 3.3v when v1 is active. alternately, the battery can be charged from in if the voltages are appropriate for the cell type. MAX1586 max1587 max1724 ezk30 main power 1n4148 murata lqh32c 10 h 1-cell nimh rechargeable backup battery 10k ? in bkbt gnd batt lx shdn out v7 4.7 f 4.7 f 1 f 10 f 3.0v figure 8. a 1-cell nimh battery can provide backup by boost- ing with a low-power dc-dc converter. a series resistor-diode trickle charges the battery when the main power is on.
MAX1586a/MAX1586b/max1587a high-efficiency, low-i q pmics with dynamic core for pdas and smart phones 28 ______________________________________________________________________________________ active. in addition to biasing v7, the rechargeable bat- tery may be required to also power other supplies. rechargeable nimh backup battery in some systems, a nimh battery may be desired for backup. usually this requires multiple cells because the typical nimh cell voltage is only 1.2v. by adding a small dc-dc converter (max1724), the low-battery voltage is boosted to 3v to bias bkbt (figure 8). the dc-dc converter? low operating current (1.5? typ) allows it to remain on constantly so the 3v bkbt bias is always present. a resistor and diode trickle charge the nimh cell when the main power is present. pc board layout and routing good pc board layout is important to achieve optimal performance. conductors carrying discontinuous cur- rents and any high-current path should be made as short and wide as possible. a separate low-noise ground plane containing the reference and signal grounds should connect to the power-ground plane at only one point to minimize the effects of power-ground currents. typically, the ground planes are best joined right at the ic. keep the voltage feedback network very close to the ic, preferably within 0.2in (5mm) of the fb_ pin. nodes with high dv/dt (switching nodes) should be kept as small as possible and should be routed away from high-impedance nodes such as fb_. refer to the MAX1586 or max1587 evaluation kit data sheets for a full pc board example. increasing v3 (vcc_core) voltage range the programmable v3 output voltage range can be increased by adding two resistors as shown in figure 9. output accuracy with 1% resistors is ?.8%. chip information transistor count: 13,958 process: bicmos top view rso srad lx3 pg3 v4 on45 on2 v5 in45 pv3 v7 v1 slpin v2 fb2 cc2 pok scl bkbt fb1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 pg2 in ramp ref byp lx2 pv2 pwm3 sda slp pv1 lx1 pg1 on1 on3 fb3 cc3 mr cc1 thin qfn 6mm 6mm max1587aetl gnd rso srad lx3 pg3 v4 on4 on2 on5 on3 v5 in45 pv3 v7 v1 slpin v2 fb2 cc2 cc1 pok scl bkbt fb1 lb1 pg2 in ramp ref byp lx2 pv2 lbo pwm3 sda slp pv1 lx1 pg1 in6 v6 on6 on1 fb3 cc3 mr dbi thin qfn 7mm 7mm MAX1586aetm MAX1586betm gnd dbo 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 pin configurations pv3 step-down pwm reg3 r24 values: r24 = 3.32k ? , v3: 0.73v to 1.55v, 26mv/step r24 = 5.11k ? , v3: 0.75v to 1.60v, 27mv/step r24 = 7.5k ? , v3: 0.78v to 1.65v, 28mv/step lx3 pg3 fb3 v3 vcc_core to batt r25 100k ? r24 MAX1586 max1587 figure 9. adding r24 and r25 to increase core voltage programming range
MAX1586a/MAX1586b/max1587a high-efficiency, low-i q pmics with dynamic core for pdas and smart phones ______________________________________________________________________________________ 29 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) qfn thin 6x6x0.8 .ep s e e l l a1 a2 a e/2 e d/2 d e2/2 e2 (ne-1) x e (nd-1) x e e d2/2 d2 b k k l c l c l c l c l d 1 2 21-0141 package outline 36,40l thin qfn, 6x6x0.8 mm
MAX1586a/MAX1586b/max1587a high-efficiency, low-i q pmics with dynamic core for pdas and smart phones 30 ______________________________________________________________________________________ 8. coplanarity applies to the exposed heat sink slug as well as the terminals. 6. nd and ne refer to the number of terminals on each d and e side respectively. 5. dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 9. drawing conforms to jedec mo220. 7. depopulation is possible in a symmetrical fashion. 3. n is the total number of terminals. 2. all dimensions are in millimeters. angles are in degrees. 1. dimensioning & tolerancing conform to asme y14.5m-1994. notes: 10. warpage shall not exceed 0.10 mm. d 2 2 21-0141 package outline 36, 40l thin qfn, 6x6x0.8 mm package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
MAX1586a/MAX1586b/max1587a high-efficiency, low-i q pmics with dynamic core for pdas and smart phones ______________________________________________________________________________________ 31 32, 44, 48l qfn .eps proprietary information approval title: document control no. 21-0144 package outline 32, 44, 48l thin qfn, 7x7x0.8 mm 1 c rev. 2 e l e l a1 a a2 e/2 e d/2 d detail a d2/2 d2 b l k e2/2 e2 (ne-1) x e (nd-1) x e e c l c l c l c l k dallas semiconductor package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
MAX1586a/MAX1586b/max1587a high-efficiency, low-i q pmics with dynamic core for pdas and smart phones maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 32 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2003 maxim integrated products printed usa is a registered trademark of maxim integrated products. proprietary information document control no. approval title: c rev. 2 2 21-0144 package outline 32, 44, 48l thin qfn, 7x7x0.8 mm dallas semiconductor package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)

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